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More work on wiegand.

master
flabbergast 6 years ago
parent
commit
a3d0614e06
  1. 53
      ld/MK20DX256BLDR8.ld
  2. 3
      projects/wiegand_2/Makefile
  3. 20
      projects/wiegand_2/chconf.h
  4. 94
      projects/wiegand_2/flash.c
  5. 15
      projects/wiegand_2/flash.h
  6. 2
      projects/wiegand_2/halconf.h
  7. 5
      projects/wiegand_2/main.c
  8. 65
      projects/wiegand_2/wiegand.c
  9. 27
      projects/wiegand_2/wiegand.h

53
ld/MK20DX256BLDR8.ld

@ -1,53 +0,0 @@
/*
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio.
This file is part of ChibiOS.
ChibiOS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* MK20DX256 memory setup (8k bootloader section).
*/
MEMORY
{
flash : org = 0x00002000, len = 256k - 0x2000
ram0 : org = 0x20000000 - 64k / 2 , len = 64k
ram1 : org = 0x00000000, len = 0
ram2 : org = 0x00000000, len = 0
ram3 : org = 0x00000000, len = 0
ram4 : org = 0x00000000, len = 0
ram5 : org = 0x00000000, len = 0
ram6 : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0
}
/* RAM region to be used for Main stack. This stack accommodates the processing
of all exceptions and interrupts*/
REGION_ALIAS("MAIN_STACK_RAM", ram0);
/* RAM region to be used for the process stack. This is the stack used by
the main() function.*/
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
/* RAM region to be used for data segment.*/
REGION_ALIAS("DATA_RAM", ram0);
/* RAM region to be used for BSS segment.*/
REGION_ALIAS("BSS_RAM", ram0);
/* RAM region to be used for the default heap.*/
REGION_ALIAS("HEAP_RAM", ram0);
INCLUDE rules_kinetis_bldr.ld

3
projects/wiegand_2/Makefile

@ -5,7 +5,7 @@
# Compiler options here.
ifeq ($(USE_OPT),)
USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16
USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16
endif
# C specific options here (added to USE_OPT).
@ -191,6 +191,7 @@ CSRC = $(STARTUPSRC) \
$(BOARDSRC) \
main.c \
usbcfg.c \
flash.c \
wiegand.c \
$(CHIBIOS)/os/hal/lib/streams/chprintf.c

20
projects/wiegand_2/chconf.h

@ -134,7 +134,7 @@
* @note This is not related to the compiler optimization options.
* @note The default is @p TRUE.
*/
#define CH_CFG_OPTIMIZE_SPEED TRUE
#define CH_CFG_OPTIMIZE_SPEED FALSE
/** @} */
@ -328,13 +328,23 @@
#if defined(F042)
// #define CH_DBG_STATISTICS FALSE
// #define CH_DBG_SYSTEM_STATE_CHECK TRUE
// #define CH_DBG_ENABLE_CHECKS TRUE
// #define CH_DBG_ENABLE_ASSERTS TRUE
// #define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_NONE
// #define CH_DBG_TRACE_BUFFER_SIZE 128
// #define CH_DBG_ENABLE_STACK_CHECK TRUE
// #define CH_DBG_FILL_THREADS FALSE
// #define CH_DBG_THREADS_PROFILING FALSE
#define CH_DBG_STATISTICS FALSE
#define CH_DBG_SYSTEM_STATE_CHECK TRUE
#define CH_DBG_ENABLE_CHECKS TRUE
#define CH_DBG_ENABLE_ASSERTS TRUE
#define CH_DBG_ENABLE_CHECKS FALSE
#define CH_DBG_ENABLE_ASSERTS FALSE
#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_NONE
#define CH_DBG_TRACE_BUFFER_SIZE 128
#define CH_DBG_ENABLE_STACK_CHECK TRUE
#define CH_DBG_TRACE_BUFFER_SIZE 4
#define CH_DBG_ENABLE_STACK_CHECK FALSE
#define CH_DBG_FILL_THREADS FALSE
#define CH_DBG_THREADS_PROFILING FALSE

94
projects/wiegand_2/flash.c

@ -0,0 +1,94 @@
/*
* (c) 2016 flabbergast <s3+flabbergast@sdfeu.org>
* Licensed under the Apache License, Version 2.0.
*/
/*
* Most of the code is from STM32F0x2 datasheet examples.
*/
/* WARNING WARNING WARNING
*
* This code is *dangerous*! It can potentially damage the firmware.
*
* The flash has a relatively low guaranteed number of erase operations
* (on the order of thousands).
*
* I would recommend calling these with IRQs and any other possible
* interruptions disabled, so as not to interrupt the operations,
* as flash access during them can generate HardFaults.
*/
#include "ch.h"
#include "hal.h"
#if defined(F042)
void flash_unlock(void) {
/* (1) Wait till no operation is on going */
/* (2) Check that the Flash is unlocked */
/* (3) Perform unlock sequence */
while((FLASH->SR & FLASH_SR_BSY) != 0) { /* (1) */
/* For robust implementation, add here time-out management */
}
if((FLASH->CR & FLASH_CR_LOCK) != 0) { /* (2) */
FLASH->KEYR = FLASH_KEY1; /* (3) */
FLASH->KEYR = FLASH_KEY2;
}
}
void flash_lock(void) {
FLASH->CR |= FLASH_CR_LOCK;
}
void flash_erasepage(uint32_t page_addr) {
/* (1) Set the PER bit in the FLASH_CR register to enable page erasing */
/* (2) Program the FLASH_AR register to select a page to erase */
/* (3) Set the STRT bit in the FLASH_CR register to start the erasing */
/* (4) Wait until the BSY bit is reset in the FLASH_SR register */
/* (5) Check the EOP flag in the FLASH_SR register */
/* (6) Clear EOP flag by software by writing EOP at 1 */
/* (7) Reset the PER Bit to disable the page erase */
FLASH->CR |= FLASH_CR_PER; /* (1) */
FLASH->AR = page_addr; /* (2) */
FLASH->CR |= FLASH_CR_STRT; /* (3) */
while((FLASH->SR & FLASH_SR_BSY) != 0) { /* (4) */
/* For robust implementation, add here time-out management */
}
if((FLASH->SR & FLASH_SR_EOP) != 0) /* (5) */ {
FLASH->SR |= FLASH_SR_EOP; /* (6)*/
} else {
/* Manage the error cases */
}
FLASH->CR &= ~FLASH_CR_PER; /* (7) */
}
void flash_write16(uint32_t flash_addr, uint16_t data) {
/* (1) Set the PG bit in the FLASH_CR register to enable programming */
/* (2) Perform the data write (half-word) at the desired address */
/* (3) Wait until the BSY bit is reset in the FLASH_SR register */
/* (4) Check the EOP flag in the FLASH_SR register */
/* (5) clear it by software by writing it at 1 */
/* (6) Reset the PG Bit to disable programming */
FLASH->CR |= FLASH_CR_PG; /* (1) */
*(__IO uint16_t*)(flash_addr) = data; /* (2) */
while((FLASH->SR & FLASH_SR_BSY) != 0) /* (3) */ {
/* For robust implementation, add here time-out management */
}
if((FLASH->SR & FLASH_SR_EOP) != 0) /* (4) */ {
FLASH->SR |= FLASH_SR_EOP; /* (5) */
} else {
/* Manage the error cases */
}
FLASH->CR &= ~FLASH_CR_PG; /* (6) */
}
uint16_t flash_read16(uint32_t addr) {
return *(uint16_t *)(addr);
}
#else /* !F042 */
#error "Flash functions not implemented."
#endif

15
projects/wiegand_2/flash.h

@ -0,0 +1,15 @@
/*
* (c) 2016 flabbergast <s3+flabbergast@sdfeu.org>
* Licensed under the Apache License, Version 2.0.
*/
#ifndef _FLASH_H_
#define _FLASH_H_
void flash_unlock(void);
void flash_lock(void);
void flash_erasepage(uint32_t page_addr);
void flash_write16(uint32_t flash_addr, uint16_t data);
uint16_t flash_read16(uint32_t addr);
#endif /* _FLASH_H_ */

2
projects/wiegand_2/halconf.h

@ -313,7 +313,7 @@
* buffers.
*/
#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)
#define SERIAL_USB_BUFFERS_SIZE 256
#define SERIAL_USB_BUFFERS_SIZE 128
#endif
/*===========================================================================*/

5
projects/wiegand_2/main.c

@ -163,14 +163,13 @@ int main(void) {
usbConnectBus(serusbcfg.usbp);
/*
* Normal main() thread activity, in this demo it does nothing except
* sleeping in a loop and check the button state.
* The main loop.
*/
while(true) {
if((palReadPad(BUTTON_GPIO, BUTTON_PIN) == BUTTON_ACTIVE) && (OUTPUT_CHANNEL.config->usbp->state == USB_ACTIVE)) {
/* sdWrite(&OUTPUT_CHANNEL, (uint8_t *)"hello world\r\n", 13); */
// chprintf((BaseSequentialStream *)&OUTPUT_CHANNEL, "Hello world\r\n");
chnPutTimeout(&OUTPUT_CHANNEL, 'W', TIME_IMMEDIATE);
chnPutTimeout(&OUTPUT_CHANNEL, 'W', TIME_IMMEDIATE);
wieg_send(wieg_test_buf, 26);
led_blink = 1;
chThdSleepMilliseconds(200);

65
projects/wiegand_2/wiegand.c

@ -7,6 +7,7 @@
#include "hal.h"
#include "usbcfg.h"
#include "flash.h"
#include "wiegand.h"
/*===========================================================================
@ -18,6 +19,8 @@ volatile uint8_t wieg1_reading_sequence = 0;
uint8_t wieg1_buffer[100];
volatile uint8_t wieg1_buffer_pos = 0;
volatile uint16_t print_mode;
#if WIEG_HAS_2
volatile systime_t wieg2_last_pulse_time;
volatile uint8_t wieg2_reading_sequence = 0;
@ -25,46 +28,29 @@ uint8_t wieg2_buffer[100];
volatile uint8_t wieg2_buffer_pos = 0;
#endif
// void phex4(BaseChannel *chn, uint8_t c) {
// chnPutTimeout(chn, c + ((c < 10) ? '0' : 'A' - 10), TIME_IMMEDIATE);
// }
// #define phex4(chn, c) chnPutTimeout(chn, c + ((c < 10) ? '0' : 'A' - 10), TIME_IMMEDIATE)
// void phex(BaseChannel *chn, uint8_t c) {
// phex4(chn, c >> 4);
// phex4(chn, c & 15);
// }
// #define phex(chn, c) phex4(chn, (c>>4)); phex4(chn, (c&15))
// void phex16(BaseChannel *chn, uint32_t c) {
// phex(chn, (uint8_t)(c>>8));
// phex(chn, (uint8_t)c);
// }
// #define phex16(chn, c) phex(chn, (uint8_t)(c>>8)); phex(chn, (uint8_t)c)
// void phex24(BaseChannel *chn, uint32_t c) {
// phex16(chn, (uint32_t)((c>>8)&0xFFFF));
// phex(chn, (uint8_t)c);
// }
// #define phex24(chn, c) phex16(chn, (uint32_t)((c>>8)&0xFFFF)); phex(chn, (uint8_t)c)
// void phex32(BaseChannel *chn, uint32_t c) {
// phex16(chn, c>>16);
// phex16(chn, c&0xFFFF);
// }
// #define phex32(chn, c) phex16(chn, (c>>16)); phex16(chn, c&0xFFFF)
/*===========================================================================
* Read/write mode in flash.
*===========================================================================*/
uint16_t read_print_mode(void) {
uint16_t mode;
mode = flash_read16(FLASH_ADDR);
if((mode & MODE_SIGNATURE) == MODE_SIGNATURE) {
return( mode & 0xFF );
} else {
return( MODE_DEFAULT );
}
// void pent(BaseChannel *chn) {
// chnPutTimeout(chn, '\r', TIME_IMMEDIATE);
// chnPutTimeout(chn, '\n', TIME_IMMEDIATE);
// }
}
// #define pent(chn) chnPutTimeout(chn, '\r', TIME_IMMEDIATE); chnPutTimeout(chn, '\n', TIME_IMMEDIATE);
/* Use sparingly */
void write_print_mode(uint16_t mode) {
osalSysLock();
flash_unlock();
flash_erasepage(FLASH_ADDR);
flash_write16(FLASH_ADDR, (mode&0xFF)|MODE_SIGNATURE );
flash_lock();
osalSysUnlock();
}
/*===========================================================================
* Interrupt callbacks.
@ -193,6 +179,8 @@ void wieg_process_message(uint8_t* buf, uint8_t n) {
} else {
// couldn't decode
chnWriteTimeout(&OUTPUT_CHANNEL, (const uint8_t *)"err:", 4, TIME_IMMEDIATE);
phex(&OUTPUT_CHANNEL,n);
chnPutTimeout(&OUTPUT_CHANNEL, ':', TIME_IMMEDIATE);
uint8_t i;
for(i=0; i<n; i++) {
chnPutTimeout(&OUTPUT_CHANNEL, '0'+buf[i], TIME_IMMEDIATE);
@ -289,6 +277,7 @@ void wieg_init(void) {
palSetPadMode(WIEG2_IN_DAT0_GPIO, WIEG2_IN_DAT0_PIN, WIEG2_PINS_MODE);
palSetPadMode(WIEG2_IN_DAT1_GPIO, WIEG2_IN_DAT1_PIN, WIEG2_PINS_MODE);
#endif /* WIEG_HAS_2 */
print_mode = read_print_mode();
#if (WIEG_SHOULD_RECEIVE)
chThdCreateStatic(waWieg1Thr, sizeof(waWieg1Thr), NORMALPRIO, Wieg1Thr, NULL);
#if WIEG_HAS_2

27
projects/wiegand_2/wiegand.h

@ -12,17 +12,30 @@
void wieg_init(void);
void wieg_send(uint8_t* buf, uint8_t n);
// void phex4(BaseChannel *chn, uint8_t c);
// void phex(BaseChannel *chn, uint8_t c);
// void phex16(BaseChannel *chn, uint32_t c);
// void phex24(BaseChannel *chn, uint32_t c);
// void phex32(BaseChannel *chn, uint32_t c);
// void pent(BaseChannel *chn);
bool wieg_is_26(uint8_t *buf, uint8_t n);
uint32_t wieg_decode_26(uint8_t *buf);
uint16_t read_print_mode(void);
void write_print_mode(uint16_t mode);
extern volatile uint8_t led_blink;
extern volatile uint16_t print_mode;
#define MODE_SIGNATURE 0xBE00
#define MODE_ERR (1<<0)
#define MODE_26 (1<<1)
#define MODE_34 (1<<2)
#define MODE_DEBUG MODE_ERR|MODE_26|MODE_34
#define MODE_DEFAULT MODE_26|MODE_34
#if defined(F042)
/* Address - beginning of the last 1k page (on 32kB MCUs) */
#define FLASH_ADDR 0x08007C00
#endif /* F042 */
/*===========================================================================
* Pin definitions.
*===========================================================================*/
@ -88,7 +101,7 @@ extern volatile uint8_t led_blink;
#define WIEG1_PINS_MODE PAL_MODE_INPUT
#define WIEG1_PINS_OUTPUT_MODE PAL_MODE_OUTPUT_OPENDRAIN
#define WIEG_HAS_2 TRUE
#define WIEG_HAS_2 FALSE
#define WIEG2_IN_DAT0_GPIO GPIOA
#define WIEG2_IN_DAT0_PORT PORTA
#define WIEG2_IN_DAT0_PIN 13

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