Assembly examples for Red-V Thing Plus (SiFive FE310-G002)
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flabbergast 930b40bef2 Add debugging info into README. 5 months ago
..
Makefile Add 06-irq-delay. 5 months ago
README.md Add 06-irq-delay. 5 months ago
macros.s Add top-of-file comments. 5 months ago
main.s Fix some bugs (write/irq). 5 months ago
memmap Add 06-irq-delay. 5 months ago
p_clock.s Add top-of-file comments. 5 months ago
p_delay.s Add top-of-file comments. 5 months ago
p_interrupts.s Fix some bugs (write/irq). 5 months ago
p_uart0.s Add top-of-file comments. 5 months ago
platform_regs.inc Add 06-irq-delay. 5 months ago
write.s Fix some bugs (write/irq). 5 months ago

README.md

06-irq-delay

Add a basic interrupt handler, in p_interrupts.s. For trying it out, there is a rewrite of delay which now uses the timer interrupt, if interrupts are enabled. Falls back to a busy loop if not.

The actual functionality is the same as 02-chase...

There are two ways interrupts can be handled by the core: either "catch-all", a single address (in mtvec) where the core jumps on any interrupt or exception; or vectored, when mtvec points to an array of addresses. However FE310 only has 3 interrupt sources at this level, namely a software interrupt (which is triggered by writing into CLINT_MSIP register, not that useful with a single hart); a timer interrupt; and an external interrupt (serviced by the PLIC block). All the peripheral irqs (uart, spi, i2c, etc...) are routed through PLIC. So, I opted for the catch-all version.

One note about CLINT_MTIME: note that this keeps counting even when the core is halted via the debugger. I suppose it's because while the main core is halted, the AON domain (where the timer lives) still happily runs.