Assembly examples for Red-V Thing Plus (SiFive FE310-G002)
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#
# p_uart0.s: basic uart0
#
# 2021 flabbergast@drak.xyz
# Unlicense: https://unlicense.org/
#
.ifdef compressed_isa
.balign 2, 0
.else
.balign 4, 0
.endif
.include "platform_regs.inc"
# UART0: RX:pin16 TX:pin17
# init
# !! need to change baud setting if the main clock changes
# clobbers: t0, t1, t2
uart_init:
li t0, GPIO_BASE # UART0 RX/TX are selected in IOF_SEL (IOF0) on Reset.
li t2, (1<<17)|(1<<16) # which bits
lw t1, GPIO_IOF_EN(t0) # set IOF_EN bits ... read existing
or t1, t1, t2 # twiddle bits
sw t1, GPIO_IOF_EN(t0) # write back
not t2, t2 # invert bits
lw t1, GPIO_IOF_SEL(t0) # clear IOF_SEL bits (tho they should be fine on Reset)
and t1, t1, t2 # twiddle bits
sw t1, GPIO_IOF_SEL(t0) # write back
li t0, UART0_BASE # setting baud rate
li t1, 139-1 # 16 MHz / 115200 Baud = 138.89
sw t1, UART0_DIV(t0)
li t1, 1
sw t1, UART0_TXCTRL(t0) # enable transmit
sw t1, UART0_RXCTRL(t0) # enable receive
ret
# emit one byte
# a0: (unsigned!) byte to send
# blocking until byte sent
# clobbers: t0, t1
uart_emit:
li t0, UART0_BASE+UART0_TXDATA
1: # repeat until accepted
amoor.w t1, a0, (t0) # (t0)->t1, then write (t0)|a0 into (t0)
bnez t1, 1b # non-zero means tx fifo full
ret
# check if ready to transmit
# returns: a0 non-zero if tx fifo full
# clobbers: t0
q_uart_emit:
li t0, UART0_BASE
lw a0, UART0_TXDATA(t0) # bit31 indicates "full"
ret
# receive a byte
# returns: a0: received byte
# blocking until available
# clobbers: t0
uart_recv:
li t0, UART0_BASE
1: # wait until we get a byte from rx fifo
lw a0, UART0_RXDATA(t0) # bit31="empty", bit7-bit0 data
bltz a0, 1b
ret
# check if there is an incoming byte waiting
# returns: a0 non-zero if rx fifo empty
# clobbers: t0
q_uart_recv:
li t0, UART0_BASE
lw a0, UART0_RXDATA(t0) # bit31 indicates "empty"...
ret # (there can be data in b7-b0 even if "empty")