Assembly examples for Red-V Thing Plus (SiFive FE310-G002)
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#
# interrupts.s: basic irq handling setup
#
# 2021 flabbergast@drak.xyz
# Unlicense: https://unlicense.org/
#
# ! when you edit the irq handler, don't forget to push/pop
# any extra registers that you use !
# - we don't use the vectored interrupt handling, so
# there is a single function that's executed on any
# interrupt or exception (which needs to make decisions
# based on mcause)
# - the address of this fn should be loaded into mtvec
#
# (SiFive FE310 only has 3 interrupt sources (sw, timer, plic),
# so any vector table would only have 3 "used" entries.)
#
.if compressed_isa
.balign 2, 0
.else
.balign 4, 0
.endif
.include "platform_regs.inc"
irq_handler:
addi sp, sp, 3*(-4)
sw ra, 2*4(sp) # x1
sw t1, 1*4(sp) # x6
sw t0, 0*4(sp) # x5
# check if it's an interrupt or an exception
csrr t0, mcause
blt t0, zero, .interrupts
## exceptions
.exceptions:
# read CSR and stall
csrr t1, mepc # tells us where it occured
# t0 still contains mcause
jal zero, .exceptions
## interrupts
.interrupts:
andi t0, t0, 0xF # FE310 only has irqs 3,7,11
srli t0, t0, 2
beq t0, zero, irq_sw_int # 3, software interrupt
srli t0, t0, 1
beq t0, zero, irq_timer # 7, timer interrupt
jal zero, irq_ext_int # 11, external interrupt
# exit
irq_handler_exit:
lw t0, 0*4(sp) # x5
lw t1, 1*4(sp) # x6
lw ra, 2*4(sp) # x1
addi sp, sp, 3*4
mret
irq_sw_int:
jal zero, irq_handler_exit
irq_timer:
# clear the interrupt by writing a high value to CLINT_MTIMECMP.h
li t0, CLINT_BASE+CLINT_MTIMECMP
li t1, 0xFFFFF000
sw t1, 4(t0)
jal zero, irq_handler_exit
irq_ext_int:
jal zero, irq_handler_exit