Assembly examples for Red-V Thing Plus (SiFive FE310-G002)
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#
# p_clock.s: functions for setting up the main clock
#
# 2021 flabbergast@drak.xyz
# Unlicense: https://unlicense.org/
#
.if compressed_isa
.balign 2, 0
.else
.balign 4, 0
.endif
.include "platform_regs.inc"
# switch to external crystal (16MHz on red-v thing)
clock_extcryst:
li t0, PRCI_BASE
1: # Wait for crystal to oscillate
lw t1, PRCI_HFXOSCCFG(t0) # hfxoscen(bit30) is on by default on reset
bgtz t1, 1b # ... hfxoscrdy(bit31): makes value negative
li t1, 0x00070df1 # 0x00060df1 | (1<<16) | (1<<17) | (1<<18)
# = Reset value | PLLSEL | PLLREFSEL | PLLBYPASS
sw t1, PRCI_PLLCFG(t0) # Select crystal as the main clock source
ret
# switch to 64MHz PLL driven by 16MHz external crystal
clock_pll_64mhz:
li t0, PRCI_BASE
1: # Wait for crystal to oscillate
lw t1, PRCI_HFXOSCCFG(t0) # hfxoscen(bit30) is on by default on reset
bgtz t1, 1b # ... hfxoscrdy(bit31): makes value negative
# Set PLL to 64 MHz (don't activate); 64 = 16 /(2^1) *(2*(31+1)) /(2^3)
li t1, 0x20df1 # pllr=1, pllf=0x1f, pllq=0x3 (reset vals)
sw t1, PRCI_PLLCFG(t0) # pllsel=0, pllrefsel=1, pllbypass=0(!)
2: # Wait for PLL to lock: plllock(bit31): sign bit
lw t1, PRCI_PLLCFG(t0)
bgtz t1, 2b
li t1, 0x30df1 # pllsel=1 (on top of the above)
sw t1, PRCI_PLLCFG(t0)
ret
# switch to 320MHz PLL driven by 16MHz external crystal
# (the board gets quite warm!)
clock_pll_320mhz:
li t0, PRCI_BASE
1: # Wait for crystal to oscillate
lw t1, PRCI_HFXOSCCFG(t0) # hfxoscen(bit30) is on by default on reset
bgtz t1, 1b # ... hfxoscrdy(bit31): makes value negative
# Set PLL to 320 MHz (don't activate); 320 = 16 /(2^1) *(2*(39+1)) /(2^1)
li t1, 0x20671 # pllr=1, pllf=0x27(!), pllq=1(!)
sw t1, PRCI_PLLCFG(t0) # pllsel=0, pllrefsel=1, pllbypass=0(!)
2: # Wait for PLL to lock: plllock(bit31): sign bit
lw t1, PRCI_PLLCFG(t0)
bgtz t1, 2b
li t1, 0x30671 # pllsel=1 (on top of the above)
sw t1, PRCI_PLLCFG(t0)
ret